The present disclosure relates to an analog-to-digital converter (ADC) and, in particular to a low power ADC.
Over the last few years, electro-optical sensors have been developed that incorporate increasingly higher resolution. Such detectors may have different operations modes or settings that need to be stored or altered.
In particular, such sensors may include a read-out integrated circuit (ROIC) that reads out the information received by an array of pixels.
Many ROICs may be used for infrared imaging and require cooling to cryogenic temperatures to improve image quality. Power dissipation on ROICs is extremely critical for these applications since current coolers have low efficiency and the entire assembly may be mobile (e.g. vehicle, airborne or space craft) where system power is limited.
Traditionally, many ROICs utilize single-slope (SS) or double-slope (DS) analog-to-digital converters.
Conventional SS-ADC designs use a comparator output that directly latches a graycode counter value into a latch (e.g., memory). One input to the comparator is a voltage ramp that begins at a stating value and then increases over time. The greycode counter begins counting and counts up as the voltage increases. The other input to the comparator is the analog value that needs to be converted to a digital value. When the ramp input has crossed (i.e., becomes greater than) the analog value, the comparator changes the graycode counter values. This change in value is directly coupled to a latch and is used to cause the greycode counter value to be stored into the latch. Such circuits generally work for their intended purposes but as discussed more fully below, such circuits may have drawbacks when used in low power environments.